A full adder is a fundamental logic circuit of numerous logic devices such as microcontrollers, processors, field programmable gate arrays (FPGAs) and many others. In general, a full adder represents an electronic circuit that has several inputs and two outputs, S (or SUM) and COUT (or CARRY-OUT). The one-bit full adder 10 (FIG. 1) includes a logic block 12 electrically coupled to a high VDD and low VSS voltage sources, three input terminals A, B and C (or carry in bit CIN) and two output terminals S and COUT. A functionality of the one-bit full adder can be described by the following logic functions:S=A⊕B⊕C=ABC+AB*C*+A*B*C+A*BC*,  (1)COUT=AB+AC+BC,  (2)where A, B and C are input numbers with C (or CIN) being derived from the previous logic block, A*, B* and C* (or CIN*) are negations (or complements) of A, B and C, respectively. A truth table for the one-bit full adder is given in Table 1.
There are a number of circuit designs of electronic blocks for performing SUM (S) and CARRY-OUT (COUT) functions. They are distinguished by the number and type of transistors, speed, voltage, power consumption, etc. These circuits are mostly built using a complimentary metal-oxide-semiconductor (CMOS) technology employing p-type and n-type of metal-oxide-semiconductor field effect transistors (MOSFETs) to perform logic functions. The CMOS-based adder circuits are volatile. They can lose their logic states when the power is off.
TABLE 1Truth table for one-bit full adderABC (or CIN)SCOUT0000000110010100110110010101011100111111
A CMOS inverter is one of key elements of the full adder circuits. FIG. 2 shows a nonvolatile CMOS inverter 20 according to a prior art. The inverter 20 includes an p-type MOS (pMOS) transistor 2P1, an n-type MOS (nMOS) transistor 2N1, and a nonvolatile magnetoresitive (MR) memory element (or magnetic tunnel junction (MTJ)) 2J1. Gates of the pMOS transistor 2P1 and the nMOS transistor 2N1 are connected in common to serve as an input terminal IN. Drains of the transistors 2P1 and 2N1 also connected in common serve as an output terminal OUT. Sources of the pMOS transistor 2P1 and the nMOS transistor 2N1 are connected to voltage sources VDD and VSS, respectively. The nonvolatile memory element 2J1 is connected to the output terminal OUT of the inverter 20 at its first end and to a memory (intermediate) voltage source VM at its second end, where VDD>VM>VSS. The source terminal of the nMOS transistor 2N1 can be connected to a grounding source GRD (VDD>VM>GRD). Moreover, the MTJ element 2J1 can also be connected to the grounding source GRD. In this case the following relation between electric potentials of the voltage sources can be observed: VDD>GRD>VSS.
The MR element 2J1 can comprise at least a free (or storage) layer 22 with a reversible magnetization direction (shown by a dashed arrow), a pinned (or reference) layer 24 with a fixed magnetization direction (shown by a solid arrow), and a nonmagnetic insulating tunnel barrier layer 26 sandwiched in-between. Resistance of the memory element 2J1 depends on a mutual orientation of the magnetization directions in the free 22 and pinned 24 layers. The resistance has a highest value when the magnetization directions are antiparallel to each other, and the lowest value when they are parallel. Hence the magnetization direction of the free layer 22 can have two stable logic states. It can be controlled by a direction of a spin-polarized current IS running through the element 2J1 in a direction perpendicular to layers surface (or plane). The direction of the current IS and hence the magnetization direction of the free layer 22 depends of the polarity of the input signal at the gates of the transistors 2P1 and 2N1.
When an input signal IN=1 (logic “1”) is applied to the common gate terminal of the transistors 2P1 and 2N1, the pMOS transistor 2P1 is “Off” and the nMOS transistor 2N1 is “On”. The spin-polarized current IS is running in the direction from the memory source VM to the source VSS. The current IS of this direction can force the magnetization direction of the free layer 22 in parallel to the magnetization direction of the pinned layer 24, which corresponds to a logic “0”. When the input signal is changed to IN=0 (a logic “0”), the pMOS transistor 2P1 turns “On” but the nMOS transistor 2N1 is “Off”. The spin-polarizing current IS is running in the opposite direction from the logic source VDD to the memory source VM. As a result, the magnetization direction of the free layer 22 can be forced in antiparallel to the magnetization direction of the pinned layer 24. This mutual orientation of the magnetizations corresponds to a high resistance state or to logic “1”. Hence, the logic value of the memory element 2J1 corresponds to a logic value at the output terminal of the conventional volatile CMOS inverter. The memory element 2J1 can provide a nonvolatile storage of the logic state of the inverter 20. The data may not be lost when the power is off.
CMOS-based adders are volatile. They can lose their data when the power is off. The present disclosure addresses to this problem.